1. Field of the Invention
The invention relates to phase locked loops (PLLs), and more particularly, to a method for automatically determining an optimal VCO frequency range in a PLL having a plurality of frequency ranges.
2. Description of the Prior Art
A phase lock loop (PLL) is a circuit that generates a periodic output signal that has a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications.
FIG. 1 shows a block diagram of a conventional charge-pump PLL 100 according to the prior art. The conventional charge-pump PLL includes a reference divider 102, a phase/frequency detector (PFD) 104, a charge pump 106, a loop filter 108, a voltage controlled oscillator 110, and a feedback divider 112. The PDF 104 compares the phase of a reference signal FREF (divided from an input signal FIN) to the phase of a feedback signal FFB and generates an error signal: either an Up signal (when the reference signal FREF leads the feedback signal FFB) or a Down signal (when the reference signal FREF lags the feedback signal FFB). The pulse width of the error signal indicates the magnitude of the phase difference between the reference signal FREF and the feedback signal FFB.
The charge pump 106 generates an amount of charge equivalent to the error signal (Up or Down) from the PFD 104. Depending on whether the error signal is an Up signal or a Down signal, the charge is either added to or subtracted from capacitors in the loop filter 108. For the purposes of this explanation, the loop filter 108 has a relatively simple design, consisting of an integrator formed by a first capacitor 114 in parallel with the series combination of a second capacitor 116 and a resistor 118, and a low-pass filter formed by the a second resistor 120 and a third capacitor 122. As such, the loop filter 108 operates as an integrator that accumulates the net charge from charge pump 106. Other, more-sophisticated loop filters are of course also possible. The resulting loop-filter voltage VTUNE is applied to the VCO 110. A voltage-controlled oscillator is a device that generates a periodic output signal (FOSC in FIG. 1), whose frequency is a function of the VCO input voltage (VTUNE in FIG. 1). In addition to being the output signal from PLL 100, the VCO output signal FOSC is used to generate the feedback signal FFB for the closed-loop PLL circuit.
If the frequency of the output signal FOSC is to be either a fraction or a multiple of the frequency of the input signal FIN, optional input and feedback dividers (102 and 112) are placed in the input and feedback paths, respectively. If this is not required, the input and feedback dividers can both be considered to apply factors of 1 to the input and feedback signals, respectively.
Due to the effect of the feedback path in PLL 100, the steady-state output signal FOSC will have a fixed phase relationship with respect to the input signal FIN. Unless some phase offset is purposely added, the phases of the input and output signals will be synchronized will minimal offset.
Voltage-controlled oscillators, such as the VCO 110 of FIG. 1, are devices that are often designed for a wide range of applications (e.g., signal frequencies from 40 KHz to 400 MHz). Such VCOs are normally designed with a number of frequency ranges (i.e., voltage in vs. frequency out), where each frequency range is only a fraction of the total operating range of the VCO. FIG. 2 shows a hypothetical set of eight frequency ranges for the VCO 110 in FIG. 1. A special digital control input VCOCTRL is used to select one of the frequency ranges. The process of selecting a VCO frequency range appropriate for a particular application is called calibration.
For low-noise PLL applications, it is important for the VCO 110 in FIG. 1 to have a relatively low gain. This implies that the slope of the curve formed by the selected VCO frequency range should be relatively low, such as those shown in FIG. 2. A particular PLL application may have a specific desired frequency or desired frequency range for the VCO. For example, in one application, the PLL may be needed to generate a nominal 100 MHz output signal. To achieve the desired PLL operations, the VCO is calibrated by selecting the appropriate frequency range (e.g., VCO=in FIG. 2) whose center frequency FCTR is close to the desired nominal PLL output frequency.
Under ideal circumstances, corresponding frequency ranges (i.e., those having the same digital control input value VCOCTR) in all VCOs of the same design would have the same center frequencies and slopes. If this were true, for a particular PLL application, the same VCO frequency range could be selected for each and every PLL instance. However, in the real world, due to variations during device fabrication, the characteristics of the frequency ranges vary from VCO to VCO. For example, the curves for the frequency ranges shown in FIG. 2 could shift up or to the right, and even have differing slopes. Nor are they all necessarily linear. As a result, for some applications, the VCOs in different PLL instances may need to be calibrated with different digital control input values VCOCTRL to select the appropriate VCO frequency ranges for the desired output frequency.
Conventionally, each VCO is tested in the factory to characterize its set of frequency ranges and to pre-determine which digital control input values are appropriate for different desired output frequencies. When a particular VCO is selected for a particular application, such as PLL 100 of FIG. 1, the appropriate calibration setting (i.e., the particular digital control input value VCTCTRL that corresponds to the desired output frequency) is permanently burned into the device by blowing fuse links. This factory testing and hard-wiring of the VCO adds to the cost of manufacturing the PLL. It also limits the operating frequency range of each PLL to the permanently selected frequency range.